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10vhdlexamples
- 10个VHDL程序实例,包括加法器,全加器、函数发生器,选择器等。
multiply
- 本文利用全加器、半加器,利用进位保留的思想,在前向割集中加入四级流水实现了乘法器的设计,提高乘法器的运算速度,并且介绍了乘法器的VHDL的程序编写过程以及代码,并给出了仿真波形-In this paper, the use of the full adder, half adder using carry-save ideological forward cutset added four water to achieve a multiplier design, to improve the
fulladder
- 关于全加器的VHDL设计文件,已做好的quartusII软件编程文件,直接下载就可以打开-About full adder VHDL design documents, quartusII software programming files have been prepared directly download can open