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jfq
- 加法器是实现两个二进制数相加运算的 基本单元电路。8 位加法器就是实现两个8 位 二进制相加,同时加上低位进位的运算电路。-Adder is to achieve the sum of two binary computing the basic unit of the circuit. 8-bit adder is to realize the sum of two 8-bit binary, at the same time together with the low binary
serial-adder
- VHDL code for adding two hard-coded 8-bit binary numbers
test_bench_8bitserialadder
- testbench for 8 bit serial binary adder
Four-serial-binary-adder
- 用Quartus II软件原理图编写四位串行二进制加法器-Principle of Quartus II software, written in four serial binary adder
ieeepapers
- An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder Architecture of adders based on speed, area and power dissipation Design of high speed hybrid carry select adder High speed Dual Mode Logic Carry Look