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verilog50%
- 本文主要介绍了50％占空比三分频器的三种设计方法，并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD，在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL design, compile results and the
AlteraQuartusI7.2
- Altera Quartus Ii 7.2 实用指南
Trafficlightscontroller
- 1， 实验题目，和实验基本要求 • • • • • • • • • • • • • • • • • • • • 2， Quartus Ⅱ的运行环境及DE2实验板简介• • • • • • 3， 电路图和线路图，电路工
lpm_shiftreg(2)
- shift register with Quartus -shift register with Quartus II
SetupModelSimQuartus
- 两篇资料中分别介绍了仿真软件ModelSim和Quartus 2的具体安装方法。-Two data simulation software were introduced ModelSim and Quartus 2 specific installation method.
USB-byteBlaster
- quartus软件的usb bityblaster安装方法-quartus 2 software usb byteblaster install
quartusII-manual
- 说明了Quartus 2的使用方法，有图可同步操作-Illustrates the use of the Quartus 2, a graph can be synchronous operation
Quartus2-User-Manual-6.0
- Quartus 2使用说明，此为简单版本，贡查一般工作使用-Quartus 2 instructions for use, this is the simple version, check the general working tribute Use
Quartus-II-User-Guide-very-detailed
- Quartus 2使用说明，此为详细版本，贡查学习使用-Quartus 2 instructions for use, this is a detailed version of the tribute investigation to learn to use
Altera.QUARTUS.II.Megacore.IP.Library.V7.2.SP2-SH
- Torrent to get a library of files which contains crack for Quartus II v7.2
DE2_NET
- DE2开发板例程源码，FPGA:EP2C35F256C6，代码基于quartus II 9.0以上的版本（随板光盘的为7.2的版本，在9.0以上的版本上编译通不过会报错）。该代码主要功能为FPGA对以太网通信，与PC机通信-In this demonstration, we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2 board. We use the
hdb3
- hdb3译码基于quartus ii 程序 基于vhdl语言编写 利用quartus7.2 进行仿真-hdb3译码基于quartus ii 程序