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m16550a_verilog_rtl
- mentor UART IP verilog源码 以通过验证.-mentor UART IP verilog source to the test.
lab3
- verilog source code for uart design
uart
- UART schematic and code
xapp341
- verilog uart for spartan 3 fpga, its great
FPGA--uart(verilog)
- verilog uart 源码，编译器ISE9.1i版本，很有用的源码-verilog uart code
FPGA---buld-gennerate
- verilog uart 源码，编译器ISE9.1i版本，很有用的源码-verilog uart code
UART
- design IP UART by Verilog, VHDL-design IP UART by Verilog, VHDL...
UART
- 基于ISE 用verilog编写的uart串口通信源码-Based on the ISE written in verilog uart serial communication source code
verilog-uart
- UART（Universal Asynchronous Receiver Transmitter，通用异步收发器）是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路，分析UART的传输时序并利用Verilog HDL语言进行建模与仿真，最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receive
uart
- RS232接口，uart用verilog语言实现-RS232 interface, uart with verilog language
uart
- 该模块是基于串口协议用verilog实现了串口的接收和发送功能。-The module is based on a serial port protocol using verilog to realize the function of receiving and sending of the serial port.