搜索资源列表
FPGA_uart
- verilog 编写的FPGA串口通信的代码，可实现串口的收发操作-FPGA serial communication code written in verilog serial transceiver operation
veriloghdl
- verilog HDL 实用教程 包含基础的概念和一些简单应用实例-the verilog HDL practical tutorial contains the concept and some simple application examples
CPLD_18b20_uart
- 温度传感器采集数据给cpld，然后由串口上传到上位机；编程语言是verilog；-Temperature sensor collected data to the the cpld, then uploaded to the host computer by serial programming language verilog
REFRESH
- VERILOG实现数码管动态刷新，开机复位后显示1234-VERILOG digital dynamic refresh, power-on reset is displayed after 1234
carrylook4bit
- carry 4-bit adder program in verilog
codlab-17-2-12
- Verilog programs- multiplexer, encoder etc
New-Folder
- it is a verilog code for masterslave flipflop
shuzishizhong-verilog
- 基于2410开发板数字时钟的开发，实现了计时，日期，跑表的功能-Based on the development of the 2410 development board digital clock, a time, date, stopwatch function
elevator-verilog
- 基于2410开发板控制电梯运行的开发，实现了电梯的基本功能-Development, the basic functions of the elevator control elevator running based on the 2410 development board
vedicmuliplier
- Vedic multiplier design in Verilog HDL
ripple-carry-array-mult
- Ripple carry array multiplier design in verilog HDL
carrysave-array-mult
- Carry save array multiplier design in verilog HDL
ModelSim_SE_Plus_v5.7F_Real_Working
- model sim simulator of vhdl and verilog codes
verilogHDL
- 夏雨闻经典Verilog HDL详介绍了verilog HDL语法规范和无数经典例程，是和初学者学习，简单易懂。-Xia Yu Wen the classic Verilog HDL detailed introduction verilog HDL syntax specification and countless classic routines, and for beginners to learn, easy to understand.
DAC-TLC5620_
- 基于verilog的硬件设计，DAC芯片TLC5620_verilog代码-The DAC chip TLC5620_verilog code verilog-based hardware design
Multiplier
- 详细介绍了给予Verilog的乘法器设计过程。-Details the the multiplier given Verilog design process.
digital-Timer
- 数字时钟，使用Verilog实现，已经调试过了-Digital clock, using Verilog implementation
Quartus_II-training-file
- Quartus 培训和使用教程，包括使用原理图输入，使用Verilog建立工程等-Quartus training file，include usingthe schametic to create project,and use the verilog file to create the project.
UART
- design IP UART by Verilog, VHDL-design IP UART by Verilog, VHDL...
UART
- 基于ISE 用verilog编写的uart串口通信源码-Based on the ISE written in verilog uart serial communication source code