搜索资源列表
dds
- 自己收集的一些关于DDS的文章，主要讲述了DDS原理以及如何利用verilog实现DDS-To collect some of their articles on the DDS, the main principle on the DDS and how to use DDS to achieve verilog
BCH15_11
- example of codec BCH(15,11)
serial1
- 串口简化verilog模型，固定波特率4.8k, 输入、输出使能输出-Verilog model of serial simplified
opencores_coding_guidelines
- Opencores.org HDL coding guideines. Useful VHDL/Verilog coding.
moukuai
- 整理的一些FPGA模块资料，是用VERILOG语言写的，希望对大家有用。-Collate information on a number of FPGA module is used VERILOG language, and I hope useful for all of us.
QuartusIIModelsim
- modelism 与Verilog的综合使用 和经典啊，FPGA绝对哟用-modelism and the integrated use of Verilog and classic ah, FPGA with absolute yo
trafficlight
- 基于quartus 6.0的课设设计，非源码，系统设计方案-Quartus 6.0 based on the design of the class-based, non-source, system design
FPGA_8051core
- FPGA中嵌入8051单片机核的具体操作方法，有图示说明。-8051 single-chip FPGA embedded in the concrete operation of nuclear, there are icons that.
shuoming
- 使用Verilog HDL进行数字逻辑设计、综合、仿真的步骤及工具软件使用简要说明.doc
multi
- This a baugh-wooley multiplier verilog code-This is a baugh-wooley multiplier verilog code
I2C_interface
- FPGA的I2C总线模拟，采用verilog HDL语言编写-I2C bus of the FPGA simulation, verilog HDL language used
DDCFPGA
- 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T recei
DigitalCircuitAnalysisCPLDsFPGAsmatlabVHDL
- This book where you can find a lot about vhdl verilog and kinds of FPGAs and CPLDs producers -This is book where you can find a lot about vhdl verilog and kinds of FPGAs and CPLDs producers
VerilogStudyNote
- 学习Verilog心得，很不错的入门文档-Verilog learning experience, very good documentation for getting started
verilogfrommit
- 麻省理工大学Verilog教程 非常使用，值得一看。里面有4个pdf教程-Verilog from MIT
HuaWeiVerilog
- 主要用来介绍如何编写高质量的verilog程序的-Is mainly used to describes how to write high-quality verilog programs
haa
- verilog is update-verilog is update.....
tut_quartus_intro_schem
- this file is a tutorial for schematic in verilog design program
full_adder_code_in_verilog
- full adder in verilog
plugin-tut_timing_verilog_Lab2
- manual for time analysis and testing the critical path in verilog FPGA using Accumulator design