本文在介绍卷积码原理和描述方式的基础上以1/2卷积码为例重点详细阐述了基于Verilog HDL 的卷积码的编器的设计-This paper introduced the convolution code on the principles and methods described in 1/2 convolutional code as an example focuses elaborated convolution based on Verilog HDL code compiled

1/2码率，64状态，卷积编码，采用格型编码，QPSK调制-Rate 1/2, 64 state convolutional coding using trellis coding, QPSK modulation