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10-jinzhi-counter
- 10进制计数器 每计数十次有一个进位，是vhdl编程的基础程序，应用于fpga cpld可编程逻辑器件-Total scores of 10 binary counter has a per carry, is the basis for vhdl programming procedures used in programmable logic devices fpga cpld
15-jinzhi-counter
- 15进制计数器 每计数十五次有一个进位，是vhdl编程的基础程序，应用于fpga cpld可编程逻辑器件-Fifth decimal counter 15 counts each have a carry, is the basis for vhdl programming procedures, programmable logic devices used in fpga cpld
GalDevicesApplicationDesign
- 手把手教你学GAL器件应用设计 在深圳，一位 CPLD(可编程逻辑器件)设计人员的工资是月薪 1万元，而且还万金 难求。现在 FPGA／CPLD／ARM等芯片设计技术已越来越多地应用在产品开发中，本文 就是您通往芯片设计殿堂的起点。 -The GAL devices application design taught you to learn
VHDL-for-beginners
- VHDL for beginners. This file contain a few pdf s about distinguishing characteristic. Needed knowledge about VHDL in FPGA/CPLD.-VHDL for beginners. This file contain a few pdf s about distinguishing characteristic. Needed knowledge about VHDL in FP
Embedded-Hardware-Training.pdf
- 本书内容非常丰富，共分为3部分。第一部分：常用电路及元件。第二部分：PROTEL DXP.第三部分：FPGA/CPLD技术。-This book is very rich, is divided into three parts. Part I: Common circuits and components. The second part:. PROTEL DXP third part: FPGA/CPLD technology.
SVPWM_FPGA_ContainSourceCode
- 广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。-Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is propose
Experience-sharing-FPGAaCPLD
- FPGA&CPLD数字电路设计经验分享，非常值得一看-Experience sharing, FPGA&CPLD digital circuit design is very worth a look
CPLDFPGA
- CPLD的详细教程，可以作为FPGA和CPLD的入门学习使用书-Lt /RTI &