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TopLevel_DualPort_Ram_XilinxCore
- Top Level Dual Port Ram Core Project, VHDL code
planta_fagner
- is a test of a verilog implementation to do a oscilloscope with dual-port RAM
HPI-Communication-Design
- 介绍了TMS320VC5402的HPI主机接口原理,以一个简单的通信程序作为例子,详细说明通过HPI 口实现5402芯片内部的16 kB 双端口RAM与AT 89 C51单片机的通信过程. -Introduces the principle of TMS320VC5402 HPI host interface, a simple communication program as an example, a detailed descr iption of the chip to achieve