Write VHDL specifications for an eight bit twisted ring counter based on each of the designs in the previous problem. Look at the synthesis report generated by the design tools (use the Spartan 2 xc2s15-cs144-6 part for this). How many fli

The code for the second version is shown below. The synthesis report indicates that this uses 4 flip flops and 11 LUTs of various types. The maximum estimated clock frequency is 200 MHz. These results are consistent with the observations m