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risc8
- 经典计算机体系结构RISC8的源代码（Verilog），包括CPU、内存、寄存器等的实现-classic computer architecture RISC8 the source code (Verilog), including CPU, memory, such as the realization Register
DDR_SDRAM_controller_verilog
- DDR SRAM控制器的verilog完整设计文档（包含有完整的verilog源代码），
FPGA-Prototyping-By-Verilog-Examples
- 本书介绍了大量的经典的FPGA开发实例，并附有源代码，是一本很难得外文书籍。-This book presents a classic instance of the FPGA development, together with the source code, it is difficult to get a foreign language books.
rmii
- rmii 以太网接口时序源代码，值得开发借鉴的哦-verilog hdl
ht_fifo
- fifo 读写代码，能够进行速率匹配，很好的源代码-verilog hdl
DDS-Verilog
- DDS设计的源代码 用于生成高精度的DDS程序 VERILOG-VERILOG DDS DDS program design source code used to generate high-precision
frequency-agility
- 本程序为捷变频信号的verilog源代码设计实现的仿真，并含有相应捷变频信号在MATLAB仿真的结果-The procedure for the Czech Republic converted signal verilog source code design and implementation of the simulation, and the Czech Republic frequency signal containing the corresponding simulation
costas-loop-in-ISE
- ISE软件中实现costas环的方案，使用语言为verilog。文件为word形式，不含有源代码，只包含实现过程及注意事项。-ISE COSTAS LOOP