My package named design DDR2 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory. It can be a separate chip or integrated into another

My package named design DDR3 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory.

In this homework, you will need to compile and simulate a System Verilog program (constraint_mode_ex.sv) which implements multiple constrained-random test. A more detailed descr iption of the program can be found below: