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or_gate1
- 入门知识：或门用VHDL语言如何描述，并正确掌握VHDL语言的规范写法-Started: VHDL language or how to describe the door, and the right to master the VHDL language specification writing
renyiboxing
- 信号发生器是一种常用的仪器，能够实现各种波形，不同频率的输出，电子测试系统的重要部件。本研究 的数字信号发生器足基于直接数字合成即DDS技术设计的，采用VHDL与C语言相结合的方法，通过查找存储 于ROM查找表中的各种标准波形数据，产牛频率Hf调并且高精度的正弦波、方波、锯齿波等常用信号，并且町 以通过修改表中的数据，实现任意信号发生器-Signal generator is a commonly used instrument to achieve a variety of wav
UART
- UART IN VHDL LANGUAGE IS NOT BEST BUT WORK -UART IN VHDL LANGUAGE IS NOT BEST BUT WORK
dianziqin
- 这是一个电子琴设计VHDL语言，供大家参考使用，在Qutars II软件上仿真实现-This is a flower design VHDL language for reference use in Qutars II software simulation to achieve
vhdl-tutorial
- The purpose of this tutorial is to describe the modeling language VHDL. VHDL includes facilities for describing logical structure and function of digital systems at a number of levels of abstraction, from system level down to the gate level. It i
Syntaxe-VHDL_files
- VHDL language for cognitive radio
AES-FPGA
- 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA