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Verilog-to-do-SD-card
- 本文档内是基于Verilog HDL的SD卡SPI模式下的读写程序，内有详细的注释，且通俗易懂。-This document is based on Verilog HDL in the SD card in SPI mode to read and write procedures, which are detailed notes, and easy to understand.
verilog
- Verilog 4*4查表法乘法器，应用广泛，速度快。-Verilog hdl。
VHDLorverilogHDL
- 选择VHDL还是verilog HDL，说明文档-Choice of VHDL or verilog HDL, documentation
QUARTUS_II_compile_and_simulate
- Verilog HDL 在QUARTUS II下的编译和仿真顺序-Verilog HDL in QUARTUS II compiler and simulation under the order of
i2c_verilog
- verilog i2c 控制源代码，包括读写控制-verilog i2c source code control
VerilogHDL
- Verilog HDL 硬件语言 生动地描述了Verilog HDL从入门到精通的经典书籍！-Verilog HDL hardware descr iption language Verilog HDL vividly from entry to the master' s classic books!
code_style
- verilog HDL code addtional style for user.
Verilog_clk
- Verilog 语言，强大的时钟，可以调时调分，设闹钟等。-Verilog hdl。
Verilog-HDL-standard
- VERILOG的编码设计规范，使你的程序容易被理解，阅读和维护-VERILOG coding design specifications, to make your program easier to understand, read and maintain
verilog-ieee.pdf.tar
- IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Descr iption Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstractio
verilog-coding-rules
- Verilog HDL可综合RTL级代码设计规范及风格-Verilog HDL RTL level code design specifications and style
Motor.asm
- 基于verilog HDL步进电机驱动程序-The verilog HDL stepper motor driver
18.uart
- 用Verilog HDL编写的uart程序，亲测可行，注释很详细！-Written using Verilog HDL uart program, pro-test is feasible, very detailed notes!
hardwired
- 掌握硬连线控制器的设计方法。掌握硬连线控制器的Verilog HDL描述方法。了解QUARTUS II硬件描述语言和原理图混合输入设计的过程。 -Master the design method of hard wired controller. Grasp the hard wired controller Verilog HDL descr iption method. To understand the process of QUARTUS II hardware descr ipti
scan-led
- 7段共阳极数码管，译码显示，Verilog HDL程序-Code based on Verilog HDL
key_debounce
- 按键去抖动，Verilog HDL语言，比较按键去抖和不去抖的区别
shizhong
- 基于Verilog HDL语言的数字时钟程序，有秒脉冲，，计数，译码显示等部分-based on Verilog HDL language,about clock
Verilog-DATAS-xiayuwen
- 3.1 引言 3.2 Verilog HDL基本结构 3.3 数据类型及常量、变量 3.4 运算符及表达式 3.5 语句 3.6 赋值语句和块语句 3.7 条件语句3.8 循环语句 3.9 结构说明语句 3.10 编译预处理语句 3.11 语句的顺序执行与并行执行 3.12 不同抽象级别的Verilog HDL模型 3.13 设计技巧-3.1 Introduction 3.2 Verilog HDL basic structure 3.3