该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0

verilog 简单易用，占用资源少。 串口收发模块。-verilog .Serial port receive & transmition module