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Performance_Comparisons_betwee
- FLL、PLL、DLL的设计与比较,在扩频通信系统中这三种环路就是关键。,FLL, PLL, DLL design and comparison, in the spread spectrum communication system in these three loops is the key.
MT9P031
- MT9p031 手册 • Micron® DigitalClarity™ imaging technology • High frame rate • Superior low-light performance • Low dark current • Global reset release, which starts the exposure of all rows simultaneously
PLL
- Practical Phase-Locked Loop Design.rar
1
- 在这篇文章中主要介绍了DSP-PLL，使用数字信号处理器完成，很好的IEEE的资料，希望有用-In this article mainly introduces the DSP-PLL, the use of digital signal processor complete, very good information on IEEE hope that useful
ams
- pll simulation in matlab
DPLL
- 数字锁相环频率合成器的设计,鉴相器、环路滤波器、数控振荡器、反馈分频器-Digital PLL frequency synthesizer, phase detector, loop filter, NCO, feedback divider
Hybrid_PLL_Design_Tutorial_Yiar_Linn
- Hybrid PLL design techniques
costas_PLL
- costas载波恢复算法 锁相环路，注释很清楚-costas carrier recovery algorithm PLL
pll
- 关于PLL 一些经典的文章，大家可以参考一下！-PLL some classic article, we can refer to it!
LPC2292
- LPC2292采用PHILIPS LPC2292微处理器，可实现高达60MHz工作频率,片内晶体振荡器和片内PLL。LPC2292是一款基于16/32位ARM7TDMI-S，并支持实时仿真和跟踪的CPU，并带有256 k字节(kB)嵌入的高速Flash存储器-LPC2292 PHILIPS LPC2292 microprocessor, can achieve up to 60MHz operating frequency, on-chip crystal oscillator
make-PLL-with-matlab
- 用matlab仿真锁相环 来实现载波同步，调频等功能-Use Matlab simulation phase-locked loop to achieve carrier synchronization, FM
MC33696
- The MC33696 is a highly integrated transceiver designed for low-voltage applications. It includes a programmable PLL for multi-channel applications, an RSSI circuit, a strobe oscillator that periodically wakes up the receiver while a data
Il-PLL-anello-ad-aggancio-di-fase
- PLL Italiano Aggancio di fase anello
pll-matlab
- 通信系统锁相环pll matlab仿真，基于微分方程的一阶、二阶锁相环-Phase-locked loop pll matlab communication system simulation, based on first-order differential equations, second-order phase-locked loop
PLL_performance-_simulation_and_design
- PLL Algorithm, Perfomance and Design
phase-detector-PLL-demo
- 要用phase detector，可到现在还不知道PLL是什么东东，不知道phase detector是如何实现的。 可叹自己没有把事物的因果分析清楚，可叹国外的人懂的比自己多。感谢国外作者的分享。-phase detector PLL demo
VL7013-VLSI
- VL7013 VLSI FOR WIRELESS COMMUNICATION OBJECTIVES: • To study the design concepts of low noise amplifiers. • To study the various types of mixers designed for wireless communication. • To study and design PLL and VCO. •
suoxianghuan
- 锁相环相关知识，包含二阶 三阶 锁相环的介绍以及编程实例汇总-Phase-locked-related knowledge, presentation and programming examples included 2nd and 3rd order PLL summary
digital-PLL
- 收集的关于数字锁相环的理论模型和分析讨论，适用于FPGA的数字电路设计。-Theoretical models and analysis and discussion about digital PLL collected for FPGA-based digital circuit design.
pll
- A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circu