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codeofvhdl2006
- 【经典设计】VHDL源代码下载～～ 其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】 基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】
用assign 语句描述的三态门
- 用assign 语句描述的三态门，三态双向驱动器，3-8 译码器，8-3 优先编码器等等,With the assign statement describing the three-state gate, three-state bi-directional drive, 3-8 decoder ,8-3 priority encoder, etc.
cmd_state
- vhdl的三态门的实现！双向的输入输出！-vhdl doors of the tri-state to achieve! Two-way input and output!
MCUBUS
- 实现MCU与单片机的通信借口 特别强调了对三态门的VHDL编程-MCU VHDL
circuit_concept
- 介绍软件驱动开发中经常使用的几个电路概念，比如三态门，高阻-Describes the software-driven development often use the concept of a few circuits, such as the tri-state gate, high resistance, etc.
fpgatri
- FPGA三态门的VHDL实现。包括2种不同的实现方法。编译环境是Quartus-VHDL 3-state gate FPGA implementation. Including two kinds of different implementations. Build environment is Quartus
zucheng
- 部分指令系统和三态门用VHDL在模型机上的实现-Part of the command system and the tri-state gate analog implementation
tristtes_test
- 三态门是FPGA 编程开发中经常遇到的一个问题,我们设计了一种正确的仿真方法，希望对大家有所帮助-Three-state gate FPGA Programming is often encountered a problem, we design a proper simulation method, we want to help
FPGAlogic
- 数据总线，三态门的逻辑分析，适合初学者 数据总线，三态门-Data bus, three-state analysis of the logic gate, suitable for beginners
combinational-logic-circuit
- 组合逻辑电路设计 实验内容 1. 二输入与门电路的实现； 2. 其他简单门电路的实现； 3. 三态门电路。 -Mix the contents of a logic circuit design experiments. Two-input AND gate circuit implementation 2 other simple gates to achieve 3 tri-state gates.
Open-collector
- 集电极开路,漏极开路,推挽,上拉电阻,弱上拉,三态门,准双向口-Open collector, open drain, push-pull, pull-up resistor, weak pull-up, three-state gate, quasi-bidirectional
tb
- 八线译码器的源文件程序用三态门控制其输出输入-entity eightbitcounter
eightbitcounter
- 8比特同步计数器，采用三态门控制其输入和输出- 8-bit up and down synchronous counter
TristateGate_lattice
- Lattice LC4128V实现三态门-Lattice LC4128V tristate gate
vhdl-Language-routine-highlights
- 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
tri_and_bus
- 三态门控制的总线原理设计图，给出了工程三态总线的基础结构。-Tri-state gate control of the bus design principle is given engineering tristate bus infrastructure.
VHDL
- 组合逻辑电路设计：基本逻辑门、三态门、译码器。-Combination logic circuit design: basic logic gates, tri-state gate decoder.
logical
- 数字逻辑三态门实验的源码，注意其中的管教约束文件-logical gates
实验1
- 用verilog语言实现译码器,包含数据流文件(Achieve decoder with verilog language, including experimental data stream file)