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RS232串口通信协议
- RS232串口通信协议，verilog实现，通过FPGA完全调通。,RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass.
rs232
- 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
RS232(verilog)
- 串口RS232通信程序，包括对串口通信原理的说明。-RS232 serial communication program, including a descr iption of the principles of serial communication.
FPGA-RS232-verilog
- fpga上的串口驱动程序，包括接收主机来的数据（deserial）和发送由FPGA产生的数据(serial).该程序的调试需要借助串口调试助手-serial port driver on the fpga, including the receiving host to the data (deserial) and send the data generated by the FPGA (serial) to pc. The program needs the serial debug deb
uart_EP3C16_FIFO
- Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
URAT
- Verilog硬件描述语言，RS232串口发送接收程序-Verilog hardware descr iption language, RS232 serial port send and receive program
RS232
- 很好用的串口通讯程序，已经通过验证，用Verilog语言编写的放心使用了！-Good use of serial communication program has been validated using Verilog language used in the rest assured!
async_transmitter
- 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
async_transmitter
- RS232串口发送模块，verilog编写，可综合-async_transmitter verilog module
RS232_project
- 串口通讯 rs232 verilog程序，一次接受传送8bits-rs232 verilog project，reciver or trancimiter 8 bits onece
RS232
- RS232_串口通信的发送端verilog源程序代码-RS232_ serial communication sender verilog source code
rs232-Quartus
- 利用verilog語法,來達成串口rs232的功能-Using verilog syntax, to achieve the functions of serial rs232
rs232
- 本设计是PC和FPGA的串口通信的程序，用的是VERILOG语言，调试成功，用户可根据自己的项目稍作改动。-The design is a PC and the FPGA' s serial communication procedures, using a VERILOG language, debugged, the user can make a little change according to their own projects.
verilog串口收发模块程序
- 基于verilogHDL语言的RS232串口收发模块程序
rs232
- rs232串口通信实验4位的串口，verilog源代码。-rs232 serial communication experiment 4 serial, verilog source code
FPGA-rs232(verilog)-2
- FPGA rs232串口收发程序，3个程序任意选择，全部可用-FPGA rs232 serial transceiver procedures, three procedures arbitrarily selected, all available
RS232
- rs232串口通讯Verilog源码，可直接用于芯片之间的串口通讯-rs232 serial communication Verilog source code can be directly used for serial communication between chips
rs232
- verily 串口rs232代码，可参数化波特率-uart code in verilog
UART-Altera
- 使用Atera FPGA CycloneII 实现串口通信，遵循RS232协议。FPGA上的模块实现了数据的接收，取补码和发送。(Achieve serial communication with FPGA, following the protocol of RS232.)
串口RS232 verilog
- 串口RS232 verilog。简单好用。