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muxplusii --vhdl 经典程序
- 用VHDL编写的数字时钟,可变宽度脉冲产生器-prepared using VHDL digital clock, Variable width pulse generator, etc.
LED.VHDL
- LED控制VHDL程序与仿真 分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序-LED control procedures and VHDL simulation briefed on the use of FPGA LED static and dynamic significantly the figures show clock control procedures
szsz
- 数字时钟vhdl实现
基于VHDL 的数字时钟
- 用VHDL实现时钟的显示，包括七段数码管和lcd1602字符液晶，可以显示十分秒，年月日
vgaclock.rar
- vga显示的数字时钟,用mif文件实现，用以大家学习交流,vga display digital clock, with the realization of mif file for them to learn from the exchange of
vhdl
- 基于vhdl的数字时钟；24制，带有定时，闹钟等功能。-VHDL-based digital clock 24 system, with time, alarm clock functions.
digitalclockvhdl
- EAD设计VHDL语言环境数字时钟数码管显示方案，包括时间设置、调整等。-VHDL language environment EAD design digital digital clock display, including time for setup, adjustment.
watch
- 功能更强大的数字时钟,有年份,月,日,时,分,秒和星期,可以调校-More powerful digital clock, there are years, months, days, hours, minutes, seconds and weeks, you can adjust the
Myshizhong
- 多功能数字时钟设计方案及电路图，以及必要分析-Multi-functional digital clock and circuit design, as well as the need to analyze the
clock
- 本文档采用VHDL语言编写了一个数字时钟的程序，该数字时钟采用24小时制计时，可以实现整点报时，时间设置，闹钟等功能。最小分辨率为1秒。-VHDL language in this document using a digital clock to prepare the procedure, the digital clock 24-hour time system, you can bring the whole point of time, time settings, alarm clo
vhdl-clock
- 数字时钟的VHDL课程设计 涉及到的几个要点有 分频模块 时分秒模块 扫描模块 显示模块-Digital Clock Design of VHDL course of a few key points related to one of those who every minute frequency module module module module scan
eetop.cn_digital_clock
- 基于VHDL的数字时钟设计课件，简单，实用-VHDL-based Digital Clock Design Courseware
eda
- eda实验时钟电路系统由秒时钟产生电路、走时电路模块、数字显示模块、校时模块、语音报时模块、工业控制模块-eda test clock circuit generated by the second clock circuit, the circuit blocks away, the digital display module, the campus module, voice timekeeping module, industrial control modules
Digitalclock_vhdl
- VHDL语言编写的数字时钟代码，环境quartus-Digital clock written in VHDL code, the environment quartusII
shuzishizhong
- 本实验实现一个能显示小时，分钟，秒的数字时钟。数字时钟-The experimental realization of a can display hours, minutes, seconds, the digital clock. Digital Clock
clock
- 基于VHDL硬件描述语言设计的多功能数字时钟的思路和技巧-VHDL hardware descr iption language based on multi-functional digital clock design ideas and techniques
数字钟
- fpga课程中用vhdl语言编写的数字钟 输出到板子上是，就是一个数字时钟
clock
- 数字时钟，用VHDL语言设计，能调时间，整点响铃(Digital clock, designed in VHDL language, can adjust the time, the whole bell ring)
数字时钟
- 基于VHDL语言编写的数字时钟程序，经验证，可以用硬件实现(Based on VHDL language digital clock program, verified, you can use hardware to achieve.)
LED控制VHDL程序与仿真
- LED控制VHDL程序与仿真 分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序。