搜索资源列表
pro001_buzzer
- 使用FPGA控制蜂鸣器的程序,用Verilog HDL设计,可以是蜂鸣器发出各种不同的声音-FPGA use buzzer control procedures, using Verilog HDL design, it is the buzzer sounded different voices
蜂鸣器VERILOG实现
- 蜂鸣器的VERILOG程序
蜂鸣器 verilog
- verilog 蜂鸣器
S1_38yima
- 利用fpga作为控制器让蜂鸣器实现播放音乐-verilog fpga
FPGA_Interface_verilog
- verilog数字接口实验程序，包括USB，矩阵键盘，蜂鸣器，串口，i2c总线接口程序实例。-verilog digital interface for experimental procedures, including the matrix keyboard, buzzer, serial, i2c bus interface program instance.
DF2C8_04_BEEP
- verilog实现蜂鸣器自动演奏一首乐曲，同时数码管显示当前演奏的简谱音符 符号。-verilog achieve buzzer automatically play a piece of music, and digital display notes the current performance of the musical notation symbols.
beep
- 一个verilog程序，写的完善，有注释，与其他蜂鸣器程序有较大改进，希望对初学者有帮助-A Verilog program, written by well-annotated, buzzers and other procedures have greater improvements in the hope to be helpful for beginners
VerilogHDL_code
- 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees
liangzhu
- 用Verilog语言编写的程序，可以运行在FPGA中，用蜂鸣器产生梁祝的曲调。-Program with the Verilog language, you can run in the FPGA, with a buzzer generating Butterfly tunes.
verilog--beep_ambulance
- altera FPGA学习测试例程序 蜂鸣器演示救护车声音 verilog beep_ambulance-altera FPGA test case study demonstrates the ambulance program buzzer sounds verilog beep_ambulance
verilog
- 蜂鸣器演奏梁柱的verilog代码，本代码已经在EP2C8的开发板上验证过，音质还不错的。-Buzzer playing the beams of the Verilog code, the code has been in the EP2C8 the development board certified, the sound quality is pretty good.
Buzzer-for-verilog
- 在FPGA上设计实现控制蜂鸣器，程序来自实验开发，验证通过。-Designed and implemented in the FPGA to control the buzzer, the program from experimental development and validation through.
verilog-HDL
- 蜂鸣器的FPGA设计，verilog语言，工程文件全-Buzzer FPGA-based design
基于FPGA实现蜂鸣器播放音乐的功能
- 使用芯片为EP2C8Q208C8N,使用普通蜂鸣器，由于频率不同可实现放歌功能，本 例设计的是《友谊地久天长》，使用Verilog语言编程，本例子有工程文件、仿 真、波形，经过测试可以使用。
Verilog-fmq
- FPGA驱动蜂鸣器，Verilog语言，蜂鸣器奏乐-FPGA driver buzzer, Verilog language, buzzer music
buzzer
- 蜂鸣器开关实例，拨码开关SW3的ON和OFF状态对应 控制蜂鸣器响或不响。(Buzzer switch example, dial code switch SW3 ON and OFF state corresponding Controls whether the buzzer sounds or does not sound.)
A4_Beep
- 使用verilog 硬件描述语言编写的蜂鸣器电路模块，希望对大家有帮助！(Using Verilog hardware descr iption language to write the key circuit module, I hope to help you!)
Buzzer
- 采用verilo语言编写的蜂鸣器，可用ISE软件来试实现(Buzzer written in verilo language, available ISE software to try to achieve)
verilog状态机
- 采用Verilog语言设计一个序列信号发生器和一个序列信号检测器，二者都以状态机模式实现。序列信号发生器输出8位宽度的序列信号“10110110”，通过数码管显示出来；序列信号发生器的输出接入序列信号检测器，检测器检测当前的输入信号，若出现目标序列信号则通过蜂鸣器输出一个声响，表示检测到有效的目标信号。(A sequence signal generator and a sequence signal detector are designed using Verilog language, b
vga
- 直接在quartus 2上运行，然后烧进试验箱，可以播放梁祝，连线就两根，一根连20MHZ，一根连蜂鸣器输入端，另一头连拓展插槽的B01，按键1控制播放、暂停，模式5，可以用点个赞，(Run it directly on quartus 2, and then burn it into the test box. You can play Liang Zhu. There are only two wires, one is 20MHz, one is buzzer input, the oth