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COUNT_100
- 使用Vhdl语言编写的FPGA应用程序,实现的内容是100进制计数器-use Vhdl language FPGA applications, realizing the contents of the 100 NUMBER
VHDL.sheji.2
- 电子时钟VHDL程序与仿真 10进制计数器设计与仿真 6进制计数器设计与仿真-electronic clock procedures and VHDL simulation Decimal counter design and simulation of six NUMBER Design and Simulation
FourBitsCounter
- 四进制计数器模块,使用VHDL语言编写,在ISE8.1中经过测试的模型-quaternary counter module, the use of VHDL language, in which ISE8.1 tested model
ctfysj
- 3-8译码器,BCD码转换10进制,计数器-3-8 decoder, 10 BCD switch 229, counter, etc.
11223344scan_led1000
- Quartus环境下的1000进制计数器的扫描显示电路-Quartus environment under the 1000 counter-band scanning display circuit
12进制计数器
- 应用VHDL语言编写十二进制计数器
masplus-works 用VHDL语言编写的八进制计数器
- 用VHDL语言编写的八进制计数器,在MASPLUS环境下编译通过,可直接使用。-Octal counter using VHDL language, compiled by MASPLUS environment can be used directly.
60jinzhijiafajishuqi
- 60进制加法计数器设计时主要采用数电知识,采用清零法和反馈置数法进行电路设计。用两片74161,采用反馈清零法进行电路设计,此时相当于设计两个加法计数器,左边的是高位片,此时的高位片在电路中相当于是一片六进制的加法计数器,逢六进清零,右边的是低位片,相当于一个十进制的加法计数器,逢十清零,此电路采用置零法与反馈清零法用multisim中进行仿真-60 Counter-band adder design using a number of major electricity knowledge,
myclk
- 两位独立数码管100进制计数器,每1秒计数一次。从0到99,到99后又回到0.-Two independent 100-band digital tube counters, every time 1 seconds count. From 0 to 99, to 99 and then back to 0.
clock
- 60进制计数器,采用十分简便的方法,能够很快速的完成计数功能。-60 M-ary counter, using a very simple way to very quickly complete the count function.
counter16
- 利用simulink制作的十六进制计数器-Simulink produced using hexadecimal counter
cout60
- 用VHDL语言编写的60进制计数器,初学者使用-VHDL language with the 60 binary counter, for beginners to use
vhdl
- 100进制计数器的设计 -100 binary counter design
ElectronicClockandsimulationwithVHDL
- 电子时钟VHDL程序与仿真。包括:10进制计数器设计与仿真,6进制计数器设计与仿真,24进制计数器设计与仿真.-Electronic Clock and simulation of VHDL program. Includes: 10 binary counter design and simulation, 6 binary counter design and simulation, 24 binary counter design and simulation.
count100
- 用VHDL语言编写的100进制计数器,计数到99后清零-VHDL language with the binary counter 100, count to 99 after the clear
16进制加减计数器
- 16进制加、减计数器,用两个数码管显示(0-15)(hex add/sub counter(show 0-15))
计数器
- 简单的硬件描述语言verilog语言描述的128进制计数器。(Simple hardware descr iption Language Verilog language described 128 binary counter.)
波浪型计数器
- 设计一个计数器,输入计数脉冲和清零信号,输出2位16进制计数值。计数器的计数规律如下:清零信号有效时输出0,计数脉冲上升沿时,输出由0递增到ff,再递减到1,然后在递增到fe,再递减到2,再递增,按如此规律反复计数。(A counter is designed, the count pulse and the zero signal are input, and the 2 - bit 16 - digit number is output. The counting rule of the c
6进制计数器
- 使用Verilog编写的六进制计数器,且可以在七段数码管显示对应的数值
16进制计数器
- 在Quartus2的平台上,利用VHDL语言实现16进制计数器的功能,仿真成功,并能在硬件平台的数码管上显示0到15的计数。