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FIFO
- 通用异步FIFO设计的verilog代码，来自于opencore-Universal Asynchronous FIFO Verilog design code, from opencore
LM3S_UART_FIFO_IntTx
- UART(通用异步收发器)\LM3S系列UART例程：FIFO中断方式发送数据-UART (Universal Asynchronous Receiver Transmitter) \ LM3S series UART routines: FIFO interrupt mode to send data
a_vhd_16550_uart_latest.tar
- 这个芯的设计是与国家半导体PC16550D兼容 UART（通用异步接收器/发送器）。一些差异：该FIFO的始终启用 不支持置顶奇偶-This core is designed to be a compatible with the National Semiconductor PC16550D UART (Universal Asynchronous Receiver/Transmitter).Some differences: The FIFO’s are always enabl
fifo
- FIFO是通过时钟来确定是同步还是异步的，同步FIFO的读写操作是通用一个时钟来控制的。另一方面。两个不同频率或者不同香味的时钟来控制异步FIFO的读写操作。 异步FIFO 跨越时钟域的同步问题-FIFO is determined by the clock is synchronous or asynchronous, synchronous FIFO read and write operations are a common clock control. on the other ha
asyn_fifo_204b_28
- 通用性异步fifo,性能非常好，推荐给大家(unverisal asyn fifo)