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1PPS
- 应用VHDL语言将高稳晶振分频得到1pps，使用GPS的1pps信号作为触发
A-Simulation-System-for-Multi-Mobile-Events-in-WS
- Sensor networks are a sensing, computing and communication infrastructure that are able to observe and respond to phenomena in the natural environment and in our physical and cyber infrastructure. In this paper, we investigate how the sensor netw
B-decoder1
- IRIG-B码的解码以及数码管显示程序，且输出1PPS信号-IRIG-B decoder program in c language,and display in segment.
IRIG-Bcode
- 本课题主要研究IRIG-B码的解码过程，并设计一个IRIG-B码的解码装置，使其能够解调出来1pps 标准秒脉冲信号-The main subject of research IRIG-B code decoding process, and to design an IRIG-B code decoding apparatus, so that it can demodulate out 1pps standard second pulse signal
Signal-1MHz-1pps
- 实现分频处理的一个模块。从输出的1MHz信号转化为1pps信号。-Achieve sub-frequency processing module. From the 1MHz signal output into 1pps signal.
Stm32_2USART
- 使用STM32(cortex-M3核)模拟GPS模块（摩托罗拉产品GT-UT ONCORE）与基站设备交换机通过双串口进行AT指令交互完成授时(cpu之systick产生1pps信号)，测试成功。-Use STM32 (cortex-M3 core) simulated GPS module (Motorola products GT-UT ONCORE) and base station equipment switches through dual serial AT commands in
main
- 对gps的1pps信号进行平滑滤波处理，然后驯服恒温晶振，得到原子钟级稳定度的信号。-1PPS on GPS signals are filtered and then tamed OCXO, get the signal level stability of atomic clock.
GPS-arm-keil
- GPS同步时钟，并利用GPS模块的1PPS秒脉冲定时输出一个开关量-GPS synchronized clock, and the use of GPS module 1PPS timing output a second pulse switch
stm32f0_gpsdo
- this is GPS disciplined oscillator source code, based on 1PPS GPS signal and NMEA protocol
pps_ketiao_rb2
- FPGA程序,使用Verilog语言生成1个脉冲可调的PPS脉冲信号。(FPGA program generates 1 PPS pulse signal, using Verilog language.)