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encode_8bl0b
- 8b10b的verilog编码程序，已经验证过没有问题，效果比以前的要好-8b10b the verilog coding process has been proven there is no problem, the effect is better than before
8B10B
- 基于VHDL的双校验位8B10B编码系统的设计，对于学习VHDL语言有一定的帮助-VHDL-based dual-parity bit 8B10B coding system for learning VHDL, there is some help
8b10b_encdec
- 8b10b编码模块的设计，用vhdl语言仿真-8b10b coding module design, simulation using vhdl language
8b10b_encdec_latest.tar
- 8b10b编码的FPGA ipcore, 8b10b编码的FPGA ipcore-The 8b10b encoding of FPGA ipcore of 8b10b coding-FPGA ipcore, 8b10b coding the FPGA ipcore of
10B-encode-by-CPLD
- 光纤通道的8B10B编码在CPLD上的实现与验证，编码器由数据字符编码、控制字符编码核Disparity运算三个模块组成。-Fibre Channel 8B10B coding on the CPLD Implementation and verification, data characters encoded by the encoder, the control character encoding nuclear Disparity computing three modules.
scrambleraencoder
- 包含16位的并行扰频器和解扰器，其方程是1+x14(x的14次方)+x15(x的15次方)，还有测试代码，另外还有自己编的8b10b编码，自己已经测试过了-Contains 16 bit parallel scrambler and descrambler, the equation is 1+ x14 + x15 , and the test code.Besides, there is 8b10b coding which is tested。
64b66b-encoder
- 64b66b编码是8b10b编码的改进版，让数据通信的速度更快-64b66b 8b10b coding is an improved version of the encoding, so that faster data communication