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ADPLL
- verilog ADPLL file with testbench.v
adpll
- 全数字锁相环 功能与74297相同 提供参数配置
ADPLL.rar
- 全数字锁相环（adpll)的部分源程序代码，是其中最重要的部分。,All-digital phase-locked loop (adpll) part of the source code, is one of the most important part.
MinWinsockSpi
- verilog ADPLL file with testbench
VCchuankou
- verilog ADPLL file with testbench
a
- ADPLL of high level phase locked loop
b
- A high-speed variable phase accumulator for an ADPLL architecture
adpll
- All digital phase locked loop based clock multiplier design. No off chip components
APL99
- An All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery
10.1.1.125.4046
- BUILDING AN RF SOURCE FOR LOW COST TESTERS USING AN ADPLL CONTROLLED BY TEXAS INSTRUMENTS DIGITAL SIGNAL
ADPLL
- 学习资料。一个关于信号处理软件ADPLL的使用说明，很有用。-Learning materials. A signal processing software ADPLL of the instructions, very useful.
a-adpll-based-on-fpga
- FPGA实现的VHDL语言的全数字锁相环-a adpll based on fpga
ADPLL-patent
- 全数字锁相环的几个专利，全部为英文，很好的参考资料-DPLL patent
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
ADPLL
- verilog语言编写的fpga的全数字锁相环ADPLL程序-Verilog language FPGA all digital phase-locked loop ADPLL program
ADPLL
- code for a counter which is used in the design of a Digital Phase Locked Loop.