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aes-vhdl 使用vhdl语言实现aes（rijndael 算法）
- 使用vhdl语言实现aes（rijndael 算法），程序整体封装成为一个package，方便调用-Using vhdl language aes (rijndael algorithm), the program as a whole package as a package, easy call
aes加密算法实现，经过FPGA验证的
- aes加密算法实现，经过FPGA验证的！,aes encryption algorithm, after FPGA validation!
aes
- verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
aes_inv_cipher_top
- aes ip core, 128 bits
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
高级加密算法
- AES加密和解密源码！-AES encryption and decryption source!
CoreAES128
- Full AES Simulation Code
RIJNDAEL_EN_TOP
- AES加密运算模块，运算速率100Mbps，请大家参考-AES encryption algorithms module, computing speed 100Mbps, please refer to
RIJNDAEL_DE_TOP
- AES解密运算模块，运算速率100Mbps，请大家参考-AES decryption computing module, computing speed 100Mbps, please refer to
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
aes
- vhdl implementation of the AES encryption algorithm
aes
- 实现了AES在赛灵思器件上的加密程序 我已经调试过完全正确-Xilinx achieved in AES encryption device debugging process I have been absolutely correct
freehdl-0.0.6.tar
- inplementation of AES vhdl The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm
AES
- This the source code of AES algorithm which is used in network security.-This is the source code of AES algorithm which is used in network security.
aes
- 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
AES!
- AES algorithm very good code tested in xilinx ise tool
AES
- AES implementation in VHDL@!
AES
- 详细描述了AES加密算法的过程及S盒变换，用VHDL语言描述，通俗易懂-AES encryption algorithm is described in detail the process and transform S box, with the VHDL language to describe, easy to understand
aes-vhdl
- this file contains vhdl code for aes
aes-master
- aes master by vhdl code and decode