搜索资源列表
array1dprj
- Array cla
le02
- nehe opengl 第二课-nehe opengl second cla
16bit-CLA
- 16 bit carry look ahead adder verilog code
adder
- 运用VHDL语言实现四位超前进位加法器。-VHDL language using the four CLA.
adder_32
- 超前进位加法器是通常数字设计所必备的，本程序为32位超前进位加法器-CLA is usually necessary for digital design, the procedure for 32-bit CLA
16bitCLA
- 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
CLA.VHDL.CODE
- cla vhdl code with a picture files.
ADDER(2)
- simple 16-bet CLA adder
adder
- 8位cla，采用for结构，可以扩张成32位或者16位-8 cla, used for the structure, you can expand into a 32-bit or 16-bit
4
- simple code based on verilog shifter , cla ,clg , ALU , PC
cla
- a cla coding in verilog
cla-adder
- cla adder code in vhdl
CLA-CCSv3.3
- F28035的DSP，CCS3.3应用环境的配置，可以在一台电脑上同时打开主CPU和CLA的调试界面，对于使用CLA的并且不习惯使用新版ccs4开发环境的用户很有用！-F28035 the DSP, CCS3.3 application environment configuration on a computer at the same time open the main CPU and CLA debug interface, users not accustomed to using n
CLA-CCSv4.x
- F28035DSP，在CCS4环境下的配置，可以同时调试主CPU和CLA-F28035DSP, in the environment of CCS4 configuration, can debug the main CPU and CLA
32-bit-cla-adder
- This a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).-This is a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).
Memetic-CLA-PSO
- Memetic CLA PSO: A Hybrid Model for Optimization
CLA
- CLA adder:use vhdl to write the carry-lookahead adder which is a type of adder used in digital logic-CLA adder
cla-pso
- Coordination Design PSS and TCSC Controller for Power System Stability Improvement Using CLA-PSO Algorithm
cla
- CLA A dder Generator CLA A dde r Gen erator CLA Adder Gene ra t or CLA Adder Gen er ator
CLA代码
- 计数器跳跃进位加法器CLA代码，加法器计数器(adder with four 8-bit groups. 8-bit adder will have two 4-bit groups.)