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adder_ahead8bit
- 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
16bit-CLA
- 16 bit carry look ahead adder verilog code
adder
- 运用VHDL语言实现四位超前进位加法器。-VHDL language using the four CLA.
16bitCLA
- 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
128bitCLA
- 128位CLA 采用kogge-stone tree算法 经modlesim验证正确-128-bit CLA using kogge-stone tree algorithm as the right to verify modlesim
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
CLA.VHDL.CODE
- cla vhdl code with a picture files.
ADDER(2)
- simple 16-bet CLA adder
adder
- 8位cla，采用for结构，可以扩张成32位或者16位-8 cla, used for the structure, you can expand into a 32-bit or 16-bit
cla
- Carry Look ahead adder
16bit-CLA
- a 16 bit carry look ahead adder verilog code
CLA
- carry look ahead adder
adder-VerilogHDL
- 各种加法器的VerilogHDL语言编写的包括普通加法器，串行进位加法器，超前进位加法器等-Adder VerilogHDL various languages, including ordinary adder, serial carry adder, CLA, etc.
cla-adder
- cla adder code in vhdl
32-bit-cla-adder
- This a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).-This is a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).
CLA
- CLA adder:use vhdl to write the carry-lookahead adder which is a type of adder used in digital logic-CLA adder
8bit-CLA
- 8bit carry look ahead adder for software testing
fast-Cla
- fast Carry look ahead adder
cla
- CLA A dder Generator CLA A dde r Gen erator CLA Adder Gene ra t or CLA Adder Gen er ator
CLA代码
- 计数器跳跃进位加法器CLA代码，加法器计数器(adder with four 8-bit groups. 8-bit adder will have two 4-bit groups.)