VHDL编写计算器，功能包括：加，减，乘，除。通过keypad输入及输出-Calculator written with VHDL

用VHDL编写的计算器，供下载到学习板上使用，芯片型号请在工程中查看。可以实现加减与或比较-Written by VHDL calculator, available for download to learn to use the board, the chip model in the project view. Comparison of addition and subtraction can be achieved with or

用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.