搜索资源列表
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
DCM_12M_1M
- xilinx下DCM输出12Mhz和1Mhz-Verilog DCM xilinx ISE
dcm_IP
- 这是一个用verilog语言编写的程序，利用了自带的DCM IP核，可以做练习用-This is a program written in verilog using a built-in DCM IP core, you can do the exercises with...
mydcm1
- 基于verilog的FPGA里dcm模块分频偏移程序-dcm Frequency offset
DCM
- CCD SENSOR 驱动信号发生器，基于VERILOG HDL-CCD SENSOR driving signal generator, based on VERILOG HDL
wtut_ver.ZIP
- 码表程序，完整的verilog工程文件，完整的工程设计流程，包含时序约束，ip核的嵌入，以及DCM模块的使用-Stopwatch program, complete verilog project file, complete engineering design process, including the timing constraints, ip nuclear embedding, as well as the use of DCM module
sss
- 使用Verilog语言编写源代码.调用一些基本的IP核，如DCM模块、DDS模块ChipScope模块、乘法器模块等来实现调制.最后通过编程并利用FPGA板子实现AM、DBS、SSB的调制。-Using Verilog language source code. Invoke some basic IP cores, such as DCM module, DDS module ChipScope modules, multiplier module to achieve modulation.
divide-freq
- 基于XILINX芯片的verilog程序。调用DCM模块，完成50MHz转换75MHz，相位偏移90°-XILINX chip based on Verilog program. Call the DCM module to complete the 50MHz conversion, 75MHz, phase shift of 90 degrees