在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制-On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control

xilinx DDR3控制器读数据控制,对读控制器进行了很好的读写封装，可以支持连续和非连续读写。-xilinx DDR3 controller reads the data controller, the read controller package to read and write well, you can support continuous and sequential read and write.

verilog基于DDR3 xilinx IP核 的DDR3的读写控制，方便学习(it is based on DDR3 IP core of xilinx)

MIG IP控制DDR3读写测试，于MIG IP核用户接口时序较复杂，这里给出扩展接口模块用于进一步简化接口时序。(MIG IP controls DDR3 reading and writing tests, and the time sequence of MIG IP kernel user interface is more complex.)