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VERILOG DDS 正弦输出
- Verilog 编写
DDS.rar
- FPGA控制AD9854的源文件，verilog，附有简单文档。,FPGA to control the AD9854 source file, verilog, with a simple document.
dds
- verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
DDS
- 我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ-Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wa
DDS
- DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
FPGA-DDS
- 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
dds
- verilog语言编写，在Quartus II里仿真DDS的产生，包括所有仿真生成的相关文件，-verilog language in the Quartus II DDS in the generation of simulation, including all documents generated by the simulation,
dds
- 直接频率合成器，采用verilog hdl-Direct frequency synthesizer using verilog hdl
DDS
- this a code for DDS in Verilog-this is a code for DDS in Verilog
dds
- DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序-ewfreytrgrwf reggwrter rgterthhrgdfs rgdgf egrthg rgreaf rtgerf srfefsf frafgsf frghrsrgwgt
DDS
- 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
DDSVerilog
- DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation
DDS
- 同时用verilog 语言编写dds原代码用于生成正余弦波，并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
dds
- 在quartus下的DDS设计，Verilog语言，可以产生正弦波、三角波、方波等，频率可调。-Under the DDS in quartus design, Verilog language, you can produce sine wave, triangle wave, square wave, frequency adjustable.
DDS
- Verilog语言实现基于DDS技术的余弦信号发生器，输出位宽16Bit-Verilog language technology based on the cosine DDS signal generator, the output bit width 16Bit
dds
- DDS数字式频率合成器 利用VERILOG实现，有modelsim仿真图-DDS digital frequency synthesizer using VERILOG realization, modelsim simulation diagram
DDS
- DDS数字频率合成的verilog代码，附有正余弦查找表等-DDS digital frequency synthesis verilog code, with a cosine look-up table, etc.
DDS
- 关于用FPGA制作的DDS源代码。用的是verilog语言，用的是xlinx的软件-Produced with the DDS on FPGA source code. Using verilog language, using xlinx software
DDS
- 能在DDS中用Verilog HDL语言实现FM,AM,FSK,ASK,PSK，结合可编程器件FGPA等等就能实现这些功能 -DDS can be used in Verilog HDL language FM, AM, FSK, ASK, PSK, etc. FGPA programmable devices can be combined to achieve these functions