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  1. fir_liujiao

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  2. 利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:93.89kb
    • 提供者:juan
  1. FIR

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  2. 实现FIR滤波,利用Verilog语言对其进行了设计 -FIR filter implementation using Verilog language design was carried out
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-17
    • 文件大小:3.94mb
    • 提供者:翁萍
  1. 34105908-Multipliers-Using-Vhdl

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  2. ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:371.41kb
    • 提供者:phitoan
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