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ref-sdr-sdram-vhdl
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
ddr_code
- 基于FPGA的DDR SDRAM控制器的VHDL硬件描述语言-FPGA-based DDR SDRAM controller VHDL hardware descr iption language
RGMII_TRANSMITTER
- This module converts 8 bit SDR flow to 4 bit DDR RGMII flow, proved on Altera Cyclone 3 devices.
RGMII_RECEIVER
- This module converts 4 bit DDR RGMII flow to 8 bit SDR flow, proved on Altera Cyclone 3 devices.