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基于FPGA的直接数字频率合成器（DDS）设计
- 基于FPGA的直接数字频率合成器（DDS）设计 （源程序）,FPGA-based direct digital synthesizer (DDS) design (source code)
FPGA.rar
- FPGA，vhdl语言的学习资料； FPGA的简单设计 dds的设计,FPGA, vhdl language learning materials FPGA design of a simple design dds
DDS.rar
- 自己在Quartus下用VHDL编写的一个DDS程序。包括寄存器，累加器，波形存储器,In Quartus using VHDL procedures for the preparation of a DDS. Including the register, accumulator, waveform memory
DDS.rar
- FPGA控制AD9854的源文件，verilog，附有简单文档。,FPGA to control the AD9854 source file, verilog, with a simple document.
FPGA-DDS-FM.rar
- DDS 调频信号发生器框图设计原理，有仿真测试结果,DDS signal generator FM Design Principle diagram
dds
- verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
dds
- 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
FPGA-DDS
- 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
FPGA-VHDL-DDS
- 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
dds
- 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
dds
- 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
DDS
- 基于DDS技术的函数波形发生器设计，适合用fpga设计波形发生器用-Based on DDS technology function waveform generator design, suitable for FPGA design with Waveform Generator
dds
- dds移相信号发生器 VHDL语言代码-dds
dds
- dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
VHDL
- DDS产生正弦波（VHDL语言）用DDS产生3MHZ的正弦波,VHDL控制语言-DDS have a sine wave (VHDL language) 3MHZ generated by the DDS sine wave, VHDL control language
VIDEO-FPGA
- 视频采集输出实例，FPGA视频采集和输出-Video Capture output examples
dds
- fpga利用dds原理，产生正弦波，简单实用，成本低-fpga using dds principle, have a sine wave
DDS-FPGA
- 基于FPGA的DDS资料！个人搜集的 可直接编译-FPGA-based DDS information!
DDS
- 毕业设计，基于FPGA的DDS设计与实现模块-FPGA DDS