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CORDIC_mixer
- FPGA可实现的，使用cordic算法的NCO模块混频模块。该模块基于cordic原理，算法中只需要加法和移位运算既可以完成信号的混频功能-FPGA can be achieved, the use of the NCO cordic algorithm module mixing module. Cordic module based on the principle, the algorithm only needs Adder and shift operator can complete
NCO_sin
- 基于FPGA的NCO设计,采用查表方法.八位地址线,一个周期采点256个,输出八位数据.
dds_new
- 驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率可以做到Hz量级-Clock driver joined the PLL, the DDS makes the clock-driven variable-.32-bit NCO makes the resolution of DDS can be done Hz magnitude
NCO
- 基于FPGA和SRAM的数控振荡器的设计与实现-SRAM-based FPGA and NCO of the design and implementation
RealizationofdigitaldownconversionbyFPGA
- 介绍在FPGA 器件上如何实现单通道数字下变频（DDC）系统。利用编写VHDL 程序和调用部分IP 核相结合的方法研究了数字下变频的FPGA 实现方法,并且完成了其主要模块的仿真和调试,并进行初步系统级验证。-Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the prepa
dspddc_R12p1
- 基于DSPbuilder搭建的DDC，里面包括CIC滤波器，FIR低通滤波器，HB半带滤波器，NCO等，实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
CarrierGen
- 用VC的程序的方法来模拟FPGA的NCO的功能-Program with VC methods to simulate the function of FPGA-NCO
ddc
- 电子科大2009-数字中频技术的研究与FPGA实现，主要是DDC的FPGA实现，NCO部分的FPGA实现！-UESTC 2009- Digital IF Research and FPGA, the FPGA implementation is mainly DDC, NCO segment FPGA to achieve!
A_digital_WaveformGenerator_and_Oscilloscope_based
- 一种基于BASYS开发板(Xilinx Spartan-3E FPGA)的波形发生器和示波器的设计，可以产生多种可调波形，并实时显示在电脑显示器或者投影仪上。波形发生器采用基于ROM的数字控制振荡器（NCO）实现，示波器采用VGA接口实时显示。-A kind of digital WaveGenerator and Oscilloscope based on tne BASYS experiment board which has a Xilinx Spartan-3E FPGA on it.T
cordic
- FPGA中数字信号发生器NCO用CORDIC实现产生正弦余弦-failed to translate
NCO
- 关于FPGA设计实现NCO，包括查找表法和CORDIC算法的改进-FPGA design and implementation on the NCO, including the look-up table method and the CORDIC Algorithm
NCO
- 基于FPGA的NCO数字化实现方法,并从原理上作了必要的分析-NCO of digital FPGA-based implementation, and made from the principle of the necessary analysis
nco
- 基于FPGA的压控震荡器，可以通过震荡器来对输入信号进行有效的分频，而且是任意的分频系数都可以-FPGA-based VCO oscillator input signal, the effective frequency division and any sub-frequency coefficients can be
DDC_FPGA
- 基于FPGA的数字下变频器（DDC）的设计,将采样得到的高速率信号变成低速率基带信号，以便进行下一步的信号处理。由NCO、数字混频器、低通滤波器和抽取滤波器四个模块组成。采用自编的加法树乘法器，提高乘法运算效率。-Design based on FPGA digital downconverter (DDC), the high-speed signal will be sampled baseband signal into a low rate for the next step in th
The-Phase-Locked-Demodulation-
- 利用Altera公司推出的FPGA开发工具DSP Builder，对锁相解调算法中的主要部件：数控振荡器(NCO)、计算反正切的CORDIC模块和FIR低通滤波器进行了单独设计和仿真，最终完成了锁相解调系统的整体设计。-Designed and simulated major components of phase-locking Demodulation Algorithm independently, including: Number Controlled Oscillator(NCO)、
NCO_test
- FPGA的压控振荡器NCO完整Verilog工程代码，测试输出1KHZ sin波。signaltap抓取没问题。-VCO NCO complete FPGA Verilog code engineering, test output 1KHZ sin wave. signaltap crawl no problem.
NCO
- 基于FPGA的DDS设计，通过外接DA转换器输出稳定的正弦波，方波和三角波，可单独产生时钟，不必借助硬件连接，包含寄存器程序，累加器程序和时钟发生电路等，以及顶层设计原理图-The DDS FPGA-based design, through an external DA converter output stable sine wave, square wave and triangular wave, can produce a single clock, without the help
gensin
- 用fpga控制da发一定带宽正弦信号，用vhdl编写，用nco-Fpga controlled by a band-da made a sinusoidal signal, written in vhdl, with nco
NCO
- 一种基于FPGA的数控振荡器技术的实现方法(FPGA implementation of NC oscillator NCO)
nco1mhz
- 使用FPGA元件中的NCO产生1MHZ频率\相位可调的输出(Use the NCO in the FPGA element to produce 1MHZ frequency \ phase adjustable output)