搜索资源列表
I2S
- 这是一个I2S接口的VHDL实现源代码，I2S是一个通用的音频接口。-This is a I2S interface VHDL source code, I2S is a generic audio interface.
DSP-I2S-DMA
- TI DSP TMS320VC5509A的SDRAM、I2S、DMA等的接口程序。-TI DSP TMS320VC5509A of SDRAM, I2S, DMA interface procedures.
I2S
- I2S（Inter-IC Sound Bus）是飞利浦公司为数字音频设备之间的音频数据传输而制定的一种总线标准。在飞利浦公司的I2S标准中，既规定了硬件接口规范，也规定了数字音频数据的格式。
I2S
- LPC23XX在keil下c语言的例子4:I2S
LPC2368-I2S
- LPC2368平台的I2S的测试实验，软件平台为KEIL.测试过。-LPC2368 platform I2S test experiment, the software platform for KEIL. Tested.
I2S
- I2S总线开发相关文档,用于语音开发与应用-I2S bus development of related documents for the development and application of voice
SPI-I2S
- spi模拟i2s，实现音频播放，网上的参考，不易找到，供大家分享-spi simulation i2s, for audio playback, online reference, easy to find for people to share
basic-ssc-i2s-at73c213-project-at91sam9260-ek-keil
- at91sam9260的i2s驱动，keil代码-i2s driver of at91sam9260
I2S
- 有关I2S接设计的一个文档，对几种方法进行了简单的讲解。-Designed on the I2S access a document on several ways to carry out a simple explanation.
I2S
- I2S BUS SPECIFICATION
basic-ssc-i2s-wm8731-project-at91sam3u-ek-gnu
- I2S WAV播放范例，使用GNU环境开发。-EXAMPLE OF I2S WAV PALY
basic-ssc-i2s-wm8731-project-at91sam3u-ek-keil
- I2S WAV 播放,使用KEIL开发环境。-EXAMPLE OF I2S PLAY
13-I2S
- 24系列的I2S使用源码，没有头文件，很有代码参考价值-24 series of I2S use source code, no header files, very useful code
I2S
- Workbench 5.30评估版软件 利用上述开发软件，核心处理器采用基于Cortex-M3核的LPC1700芯片，I2S通信。直接打开工程文件就可轻松实现调试-Workbench 5.30 evaluation version of the software development using the above software, the core Cortex-M3 processor core based on the LPC1700 chip, I2S communication
I2S
- I2S相关说明，包括信号说明，操作等，跟大家共享一下。-I2S instructions, including signal descr iption, operation, etc., to share with you about.
I2S
- NXP LPC1766 I2S配套例程 周立功开发板配套高级例程-I2S for LPC1766
lpc1768-I2S
- arm cortex m3 lpc1768-source code-I2S
LPC2300ARM-I2S
- 周立功的LPC23XX的ARM的各模块PPT资料 I2S-ZLG' s LPC23XX each module of the ARM data I2S PPT
I2S总线规则
- I2S开发开发需要知道的知识，I2S主要用来传输音频数据(I2S development and development needs to know the knowledge, I2S is mainly used to transmit audio data)
i2s
- 用Verilog实现的i2s功能，支持24bit的左右声道 接收和发送。左对齐，延迟1拍。(I2S module, Verilog I2S, up to 24-Bit Data Data Valid on Rising Edge of SCLK)