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Chapter10
- 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
I2C
- 用verilog HDL实现I2C Master Controller 的设计，包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
pic-i2c-master-test
- PIC单片机I2C通信主模式，内涵Proteus仿真内容-PIC MCU I2C master mode communications, meaning the content of Proteus simulation
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
I2C
- I2C AVR单片机使用I2C总线的例子，AVR工作于I2C的主节点模式，包含两个例子 I2C.c 以单字节模式访问I2C总路线器件AT24C02的例子程序，从中可以学习I2C总线的工作过程 AT24C02.c 调用库函数对AT24C02进行读写，可以连续多字节读写。-Single-chip I2C AVR example of the use of I2C bus, AVR job in I2C master mode node, including two examples in
I2C-Master-_-Slave-Core
- 用verilog 实现的 iic 总线编程，包括master，和slave的编程，很详细的iic总线编程-Iic-bus implemented using verilog programming, including the master, and slave programming, a very detailed iic-bus programming
i2c-example
- MICROCHIP 實現I2C的 Master 端 (Firmware) 及 Slave 端 (Hardware) 相對應的程式範例 -err
tsl2561
- 该程序是pic单片机程序，里面含有主从单片机i2c通讯程序。开发环境就是pic单片机的那个专用开发环境。单片机c程序，仅供大家参考。-The program is pic Singlechip procedure, which contains a single-chip i2c master-slave communication procedures. Development environment that is dedicated pic SCM development environm
I2C
- 基于FPGA的I2C总线主控器的设计与实现-Based on the I2C bus master FPGA Design and Implementation
wishbone_i2c_master_vhd
- wishbone i2c master vhdl code
f4520_m_s_v2
- I2C master and slave program with PIC.
s3c2410-i2c-linux-2.4-driver
- s3c2410 arm-linux-2.4.18 i2c master driver
I2C
- I2C主机端模块 具有avalon-MT总线接口 可挂载在Altera soc系统之上 使NiosII处理器具备I2C通信能力 模块由Verilog HDL编写 并经Cyclone II FPGA测试-I2C master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII I2C communication capability . This mo
i2c_master_slave_core
- I2C master/slave IP core
i2cslave_latest.tar
- hi this is i2c master in verilog
i2c
- i2c master controller, free ip
i2c_master
- 测试i2c总线的主机代码，可以测试从机的功能，很方便使用-verilog cold i2c master
I2C_code
- 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
module-i2c
- I2C MASTER CODE FOR VERILOG AND FGPA IMPLEMENTATION.I WILL SUPPLY FULL CODE IF NE-I2C MASTER CODE FOR VERILOG AND FGPA IMPLEMENTATION.I WILL SUPPLY FULL CODE IF NEEDED
an i2c master controller
- an i2c master controller written in vhdl