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fadd
- 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准
float_mul_verilog
- 浮点乘法verilog代码，浮点格式遵循 IEEE754 标准。-Float Point Multiply , im verilog
float_div_verilog
- 浮点格式遵循 IEEE754 标准。verilog设计源代码。-float point div . in verilog design.
fpu100_latest.tar
- 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
emiraga-ieee754-verilog-b7a63aa
- IEEE 754 floating point
ADS7822-data-collection
- ads7822数据采集，verilog语言实现， 采集结果转换为IEEE754 单精度浮点输出！-the ads7822 data acquisition, the Verilog language, collected results into the IEEE754 single precision floating-point output
FloatALU
- 用Verilog HDL实现的IEEE754浮点数加减乘除法器-float number alu
基于FPGA的单精度浮点数乘法器设计
- 《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and div