搜索资源列表
jtag_verilog
- verilog 实现的jtag ip模块 包括了测试程序-Verilog achieve the JTAG ip modules including test procedures
jtag.tar
- jtag的verilog 代码 包含boundary ce
jtag
- verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
用verilog编写的液晶显示程序
- 用verilog编写的液晶显示程序，已调试通过。 1、 本工程主要是设计一个LCD的控制模块，然后在LCD上显示想要显示的数据。 2、 通过JTAG口把LCD12864.sof下载到FPGA上，则LCD就会显示出要显示的数据。-Written liquid crystal display with verilog program has been through debugging. 1, this project is to design a LCD control module, a
JTAG-TAP.zip
- JTAG TAP controller verilog source code,JTAG TAP controller verilog source code
jtag
- verilog jtag源码及原理，还有debug模块。边界扫描等-verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.
jtag_uart
- 用verilog 语言写的jtag_uart程序用于实现jtag的串口通信-Using verilog language written in jtag_uart procedures used to implement the serial communication jtag
c73a2ceb-09a5-4366-83ea-78b08c6200eb
- jtag TAP控制状态机代码 verilog VHDL-jtag TAP state machine code
FLASHROM
- 利用Verilog通过JTAG口对FPGA（AP030）的 flashrom编程-JTAG port through the use of Verilog for FPGA (AP030) in flashrom Programming
JTAG
- JTAG Verilog source code
usbjtag
- 用于USB blaster下载线设计的JTAG仿真用的Verilog源码-For the USB blaster download cable design simulation using Verilog source JTAG
TAP1
- JTAG TAP statemachine verilog code
TAP2
- JTAG TAP Statemachine verilog code
TAP4
- JTAG TAP Statemachine verilog code
jtag-Verilog
- JTAG verilog code for xilinx fpga
Using-JTAG-PROMs-for-data-storage
- Xilinx FPGA的配置中，从Flash中读写用户数据，包括VHDL、Verilog程序-in configuring Xilinx FPGA,reading and writing user data from flash,including the VHDL and Verilog code
jtag tap
- JTAG顶层模块，verilog语言编写
jtag
- verilog语言编写的jtag（边界扫描模块），初学的时候可以-verilog language jtag (boundary scan module), a novice when you can look
JTAG_Example0_Verilog
- 一个Verilog的JTAG程序例子，包括完整的说明文档和源文件。(tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org))
ARM_SOC
- ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM ker