搜索资源列表
huffman
- 用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
quant
- 用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
iquant
- 用于FPGA的反量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
rle
- 用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
zigzag
- 用于FPGA的Z变化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
TS_control
- MPEG-2 TS 流嵌入控制数据的设计 TS流中的空帧很多，将某些空帧（188字节）全换为控制数据DIN（即在该空帧位置处构成一新的数据帧），按照TS流格式进行传输。TS流数据帧中的数据和控制数据不能出现丢失。-MPEG-2 TS stream control data embedded in the design of TS stream a lot of empty frames, some empty frame (188 bytes) for the control of the
Huffman
- 用于视频运动图像编码的HUFFMAN编码，可广泛运用于MPEG-Moving Picture for video coding Huffman coding, can be widely applied to MPEG
MPEG-2_TS
- MPEG2中的TS流！讲解怎么用控制信息代替空包！-MPEG2 in TS stream! Explain how to use control information in place of empty packet!
mpeg
- code to implement mpeg in vlsi
groundmotionsignalacquisitionandprocessingsystem.r
- 基于FPGA与PC机的地震动信号采集与处理系统的研究与实现-FPGA and PC-based machine ground motion signal acquisition and processing system research and implementation
DDRSDRAMControllerverilogcode
- 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Fron
mpeg
- mpeg encoder and decoder
FPGAbasedMPEG2TS
- 基于FPGA的MPEG-2TS码流实时分析与检测系统.nh-FPGA-based MPEG-2TS stream real-time analysis and detection system. Nh
MAC_MP3_Hardware
- MPeg audio encoder/decoder codes
MAC_MPEG2_AV
- MAC mpeg hardware code zip
MPEG-4_fact_sheet
- MPEG-4_fact_sheet 视频前端硬件编码，适用于摄像机，监控等设备或环境-Front-end hardware MPEG-4_fact_sheet video encoding for video cameras, surveillance equipment or the environment
auk_rtprx-v3.1.0.tar
- The Altera(R) RTP Receiver function implements a buffer for received RTP packets. Duplicated and re-ordered packets are corrected. Missing packets can be fixed using Pro-MPEG Code of Practice #3 Forward Error Correction
Pan-Davis-IEEE-MJ-1995-MPEG-Audio-Compression
- Tutorial on MPEG/Audio Compression
Cabad
- MPEG-4/AVC - H.264 CABAC decoder written in VHDL and synthesis on a Virtex 5
FPGAMP3_LUKA_Project_Proposal
- The goal of this project is to design a MPEG Layer III (MP3) player using a FPGA board. The FPGA will read MP3 source files, decode them into a 16-bit Pulse Code Modulated (PCM) output, and play the audio files through an external speaker.