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VHDL-SPI-Module.doc
- 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmit
median_filter
- 实现图像中值滤波的VerilogHDL源代码-Median_filter VerilogHDL Code
MovingAverageFilter
- This zip file contains the moving average filter code written in verilog HDL
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
mdf-code-4m-net
- median filter algorithm , VHDL code
mdf-code-xilinx
- median filter code in VHDl
mid-filter
- mid-filter 中值滤波算法的原理及核心代码 word版-mid-filter median filter and the core principles of the code word version
Median-Module
- Median Module VHDL code
filters_FPGA2
- this is vhdl code of median filter