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pwm_avalon_interface.rar
- 这是一个完整的pwm ip 核，可在sopc中实例化该核，下载即可用，绝对好使。,This is a complete nuclear pwm ip can be instantiated in SOPC in the nuclear, you can download, and absolutely so.
pwm-ip.rar
- 关于如何在SOPC中加入自定制的IP，并以PWM波为例，一步一步的进行了设置并讲解,SOPC on how to add customized IP, and the PWM wave for example, carried out step by step set up and on
PWM_LED.rar
- 基于ALTERA公司NIOSII的LED灯控PWM IP核设计,ALTERA-based company controlled NIOSII the LED lamp PWM IP-core design
pwm
- 在Quartus 9.0 下实现的PWM IP核设计，周期占空比均可调。-PWM IP core design,which period and duty is adjustable.
components
- quartus的几个IP核（PWM,RAM,I2C）-quartus several IP core (PWM, RAM, I2C)
FPGA_SOPC_PWM
- 将此文件解压缩，会得到一个"ip"目录，将此目录放入你的项目中，就可以在sopc中import到一个叫pwm的组建了。解压缩还会得到一个C语言文件，它是与硬件配合的Nios2_C代码 -Extract this file will get an " ip" directory into this directory in your project, you can import into the sopc in the formation of a called pwm.
PWM
- sopc的制作ipcore，有需要的下载啊-sopc
pwm
- 利用Verilog语言产生17路PWM波，控制17路舵机，可以作为IP核添加到AVALON总线上，在nios IDE里用C语言控制。-Using Verilog language production of 17 Road PWM signal to control 17 Servos, can be used as IP core to the AVALON bus, in the nios IDE in control with the C language.
pwm
- 用VHDL语言 描述 生成pwm的 IP核-Pwm using VHDL language to describe the generation of IP core
PWMcore
- 基于xilinx FPGA软核microblaze编写的PWM波产生IP核，在EXCD开发板上调试通过，内附UCF文件和说明-it s an IP core based on microblaze,it can produce pwm wave.
PWM
- verilog描述 PWM IP核 内部包括载波 占空比 和时能寄存器-IP kernel of PWM based on Verilog hdl
pwm
- Verilog 语言开发的PWＭ IP软核 验证实现了PWM 输出-Verilog language development of PWM IP verified to achieve a soft-core PWM output
StandardSystem_design
- 基于Avalon总线接口的PWM IP Core 设计 nios ide 环境下可调占空比和周期。-PWM IP Core
PWM
- PWM IP 核的verilog HDL代码-CODE of the PWM IP
pwm
- PWM的NIOS II IP核设计源文件，其频率和脉宽均可控-PWM IP core design source files of the NIOS II , It s frequency and pulse-width words can be controlled
PWM_IP_TEST
- 自定义PWM的IP核 符合avalon总线格式-Custom PWM IP core is in line with the avalon bus format
PWM_IP_test
- zynq-7000开发板 PWM IP核（VHDL和Verilog）-zynq-7000 PWM IP
pwm-atmel-hlcdc
- Errata: cannot use slow clk on some IP revisions.
PWM
- 使用VerilogHDL语言加上IP核产生PWM调制波，占空比和频率可调。-The PWM modulation wave, duty cycle and frequency can be adjusted by using VerilogHDL language and IP kernel..
pwm
- 自定义pwm ip核，符合AVALON总线-Custom PWM IP core, in line with the avalon bus