搜索资源列表
spi slave
- SPI 接口的VHDL和Verilog实现。slave模式
mcu-cpld-spi.mcu与cpld之间spi接口程序
- mcu与cpld之间spi接口程序，mcu为master，cpld用verilog写成slave模块,mcu with spi interface program between the CPLD, mcu for the master, cpld written using Verilog slave module
SPI_Slave
- SPI Slave example (VERILOG HDL)
verilog
- 介绍了一种SPI从机的接口verilog编码-verilog code for spi slave
spi.tar
- This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
tongxinyuanli
- 数字通信原理 曹志刚版的SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用--Digital Communication Principles of CAO Zhi-gang version of the SPI bus, under the Verilog hardware descr iption language implementation, including Master mode and slave mode of impl
VHD_Veri_spi
- 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequen
spi
- this the SPI slave module -this is the SPI slave module
verilog-SPI-Controler
- 使用Verilog语言实现的SPI控制器，包括SPI主机和从机代码。-Using the Verilog language implementation of SPI controllers, including SPI master and slave codes.
spislave_latest.tar
- SPI接口的verilog代码，本代码是从机代码。-SPI interface verilog code, the code is slave machine code.
spi
- spi slave verilog代码 spi slave verilog代码 spi slave verilog代码-spi slave verilog code spi slave verilog code spi slave verilog code
SPI-Verilog-123
- spi slave code s pi slave code spi slave code -spi slave code spi slave code spi slave code spi slave code
spi
- SPI 从机verilog设计,验证通过！-SPI interface slave verilog
Nitro-Parts-lib-SPI-master
- Nitro-Parts-lib-SPI Verilog SPI master and slave
SPI
- SPI（Serial Peripheral Interface，串行外设接口）是Motorola公司提出的一种同步串行数据传输标准，是一种高速的，全双工，同步的通信总线，在很多器件中被广泛应用。 SPI相关缩写 SS: Slave Select，选中从设备，片选。 CKPOL (Clock Polarity) = CPOL = POL = Polarity = （时钟）极性 CKPHA (Clock Phase) = CPHA = PHA = Phase = （时钟）相位
Master SPI的Verilog源代码(包括文档 测试程序)
- SPI接口的从机实现（利用verilog HDL语言）(Slave implementation of SPI interface (using Verilog HDL language))
spi master slave
- SPI master slave (fpga/verilog)
spi_verilog_master_slave_latest.tar
- spi 的verilog rtl 代码, 包括整体仿真环境，测试码等(spi master or slave verilog rtl code)
spi_8r8w
- 同时实现多个SPI从设备的连续读写，读写字节数可变化(implement multiply spi slave read/write operation, and the operation's bytes can be changed)
spi slave程序
- spi slave的verilog程序，有测试平台testbench程序，实现fpga作为salve的功能(spi slave verilog program)