RTL Code for Design of Extarnal Memory Controller for Accessing Asynchronous SRAM of size 512Kx16

verilog编写的关于使用MENTOR的MBISTArchitect进行momery的自测试代码，包含测试算法模型，SRAM,ROM模型-verilog prepared by the use of MBISTArchitect for momery MENTOR self-test code, including test algorithm model, SRAM, ROM model