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spi.rar
- 新华龙单片机spi通信代码经过测试，保证能用，包括spi存储器读写，主从模式通信,New single-chip spi communication code hualong tested to ensure the use, including memory read and write spi, master-slave mode of communication
spi
- spi master的verilog代码-Verilog code for spi master
spi
- spi总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-spi bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
LPC17xx-spi-master
- ARM LPC17xx 通过spi同步串行接口发送数据给从机。-ARM LPC17xx send datas to the slave by spi synchronous serial interface.
EVB9S12XF512E_Node1_LS
- 基于freescale MC9S12XF512 MCU，芯片自带Flexray通信控制器。可实现高达10Mb/s的Flxray通信.本程序主要功能： 1) 500ms实时中断。 2) spi master 运行于500kHz。 3) Flexray 总线以1.25Mbit/s 通信。-Based on freescale MC9S12XF512 MCU, chip communications controller Flexray own. Can achieve up to
spi.tar
- This is a verilog code used oversampled clock to implement spi slave. Also include C code for a ARM processor as the spi master-This is a verilog code used oversampled clock to implement spi slave
spi_core_open
- spi 设计 为主机设计，供大家参考,希望对大家有用-spi master design
spi
- 这是MC9S12DG128单片机spi通讯模块开发实例,该实例包含spi主从机的全部源代码,可实现双机通讯。-This is the MC9S12DG128 MCU spi communication module development instance of spi master and slave machines with all the source code, enabling two-machine communication.
spi_verilog
- 实现spi master功能，并有仿真代码和仿真结果。-To achieve spi master function, and a simulation code and simulation results.
spi.c
- tested on an STK500 with an ATmega32 with a 14.7456MHz crystal. Purpose: spi init, read & write routines without interrupt. These routines works only as an spi master.-tested on an STK500 with an ATmega32 with a 14.7456MHz crystal. Purpose:
l1ghVhVI
- The Vspi core implements an spi interface compatible with the many -- serial EEPROMs, and microcontrollers. The Vspi core is typically used -- as an spi master, but it can be configured as an spi slave as well.
spi
- c8051f120的spi接收发送 主从机模式-c8051f120 the spi master and slave mode of transmission received
spimaster
- This a verilog code for spi master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for spi master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
modelsim
- verilog spi master 的完整实验报告 仅供参考 切勿抄袭-verilog spi master
CE313-spi-master-EEPROM
- 用MPLAB的例子。CE313 spi master EEPROM-With MPLAB example. CE313 spi master EEPROM
spi-master-Core-DAC-ADC-spartan
- spi master Core for spartan (ADC, DAC) vhdl code
JN5148-spi-master-SLAVE
- JN5148 spi模式（spi主模式） 和IP 模式（spi从模式）-JN5148 spi master and spi slave（ip interface）
spi-master-P-tb
- spi master VHDL realisation Also contains TestBench
Nitro-Parts-lib-spi-master
- Nitro-Parts-lib-spi Verilog spi master and slave
spi_masterspi master 的Verilog源代码
- 实现spi主站通信功能,感兴趣的可以下载。(spi master use verilog.)