uart2bus_testbench,uart测试平台，主要运用uvm验证方法学，对uart接口、systemverilog和uvm等ic开发和验证有一个初步了解和掌握。-Uart2bus_testbench, uart test platform, the main use of uvm validation methodology, uart interface, systemverilog and uvm ic development and verification have a pre

一个UVM完整组件的测试平台，以一个简单的路由器作为例子进行UVM测试(A test platform for UVM complete components, taking a simple router as an example for UVM testing.)