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8倍频vhdl
- 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
EP2C20_TEST.rar
- 内含无刷电机驱动VHDL模块，读码盘4倍频模块，并用NIOS核实现简单无刷电机闭环控制。,Brushless motor driver includes VHDL modules, reading frequency module plate 4, and nuclear NIOS simple closed-loop control of brushless motor.
twice_freqencey
- 用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真-Verilog multiplier used directly to complete the algorithm, as a result of timing simulation quartus8.0
DCM
- ISE实现DCM组建例化，得到3倍频时钟-ISE to achieve established cases of DCM, received 3 octave clock
fq_div
- pll 的64倍频 锁相环技术用 实现倍频 从而达到对频率的分频-pll 64 multiplier PLL multiplier used to achieve so as to achieve the sub-band of frequencies
twice_clk
- 对输入时钟进行2倍频 已在modelsim中通过仿真 建议进行后仿 应用上来看 是可以使用的-the function of the module is frequency multiplication，and the module had been test and verified by modelsim,so the products can be employed with 100 ease by each consumer.think you!!!!
3fp
- 奇数分频和倍频(只需修改参数就可以实现较难得基数分频和倍频)-Odd frequency and frequency-doubling (just modify the parameters can be achieved relatively rare sub-base frequency and octave)
beipin_test
- 实现任意倍数的倍频,帮助大家解决VHDL倍频问题,-The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,
statemachine
- 基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal
4pin
- eda应用中的硬件描述语言vhdl4倍频率设计方法-beipin
pll
- 是quartus2的仿真倍频电路，用于产生倍频时钟！-Is a multiplier circuit simulation quartus
Freq_4
- 伺服电机编码器四倍频源程序，已经在工程中应用。非常有用。-it is important,it has been use in my project.i hope it is useful to everyone
pll
- 一个实现任意倍频的，输入参考频率未知的pll，已综合实现-frequency multiple rely on dpll，unknown reference input clock
CLOK
- 时钟分频。使用原有高频信号，将其10倍频，得到可用于八段数码管显示的扫描信号-Clock frequency. The use of the original high-frequency signal, frequency-doubling of its 10, the eight can be used to display the scanned digital signal
beipin
- 倍频出200M时钟，对输入脉冲进行计数测量时间间隙-produce 200M clock，count the input pulse
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
BPQ
- 倍频器-WE
multifreqvhdl
- 资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。-According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe tha
pll
- 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
chengxu
- 4位乘法器，4位除法器，K倍频的VHDL实现-Four multipliers, four dividers, K multiplier of VHDL