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Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
dct-code
- 离散余弦变换的VHDL实现，不错的代码和方法-Discrete cosine transform VHDL realization of good code and methods
1DCT_VHDL
- VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.-VHDL Behavioral Model for 1D DCT operation
63535312DCTofJPEG
- 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
mpeg2_idct_hw
- 2-D的DCT/IDCT在軟硬體上的verilog code-dct/idct source code for soc
DCT_IDCT
- verilog code for DCT and IDCT (JPEG)
DCT2
- 2 维 DCT的VHDL实现以及 测试代码 ， -2-D DCT of the VHDL implementation and test code
DCT
- Discrete Cosine transform VHDL code, with a positive transformation within the inverse transform of the test file.
wallace
- wallacw tree multiplier code in vhdl language mainy used for the multiplications in the image [processing of both dct and dwrt applications-wallacw tree multiplier code in vhdl language mainy used for the multiplications in the image [processing of