搜索资源列表
FPGA-based-design-of-DPLL
- 采用VHDL设计的全数字锁相环电路设计,步骤以及一些详细过程介绍。-VHDL design using all-digital PLL circuit design, detailed process steps and some introduction.
dds
- 基于FPGA的DDS设计,本程序采用verilog HDL语言编写,使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
pll(FPGA)
- 利用VHDL语言对FPGA进行锁相环倍频,经调试已经在开发板上实现倍频-The FPGA using VHDL language PLL frequency multiplier, the debug board has been achieved in the development of frequency
CyclonePLL
- Cyclone™ FPGA具有锁相环(PLL)和全局时钟网络,提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出,进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件,就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟,使内部工作的时钟频率比外部时钟更高,时钟延迟和时钟偏移最小,减小或调整时钟
formatter
- Actel 基本VHDl模块源代码,包括BCD、LCD、PLL等-Actel basic VHDL source code modules, including BCD, LCD, PLL, etc.
pll
- 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
PLL
- verilog PLL的代码,和PLL 的功能介绍,希望能通过,只是简单了点-verilog PLL code, and the function of PLL, the hope, but simply a point
pll
- 实现同步时采用锁相环,锁相环实现的原理,及源代码,-Implementation of the principle of phase-locked loop, and the source code,
pll
- 是quartus2的仿真倍频电路,用于产生倍频时钟!-Is a multiplier circuit simulation quartus
pll
- 一个实现任意倍频的,输入参考频率未知的pll,已综合实现-frequency multiple rely on dpll,unknown reference input clock
PLL
- 用VHDL和matlab编写的数字锁相环电路。-Matlab with VHDL and digital phase-locked loop circuit prepared.
pll
- 摘要:叙述了全数字锁相环的工作原理,提出了应用VHDL 技术设计全数字锁相环的方法,并用复杂可编程逻辑器件CPLD 予以实现,给出了系统主要模块的设计过程和仿真结果。-Abstract: This paper describes the working principle of an all-digital phase-locked loop is proposed application VHDL technical design an all-digital phase-locked loo
DPLL
- pll 的数字实现大家 支持 第一次 传-pll digital impliment
pll
- 实现了pll功能,有利于初学者学习pll,采用文本编辑的,利用quartus ii 设计的-Achieved pll function, help beginners learn pll, using a text editor, using quartus ii Design
VCO_WITH_PLL
- Voltage controlled oscillator with p-Voltage controlled oscillator with pll
PllLogicModel
- 用Verilog语言编写锁相环(PLL)的经典文章,很实用!-Verilog language with phase-locked loop (PLL) classic article, very practical!
pll
- 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
AD-PLL
- 基于VHDL的全数字锁相环的设计与实现,quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
PLL.ZIP
- the code specifies how to model a pll using vhdl code